Logo
Explore Help
Sign In
luke/yosys
Watch 1
Star 0
Fork 0
mirror of https://github.com/YosysHQ/yosys.git synced 2026-08-29 17:38:17 +02:00
Code Issues Packages Projects Releases Wiki Activity
Files
e79127fcebf9c5aed47f6f56fcfc8a4c4f98705c
yosys/techlibs
T
History
Eddie Hung e79127fceb Cleanup; reduce Module::derive() calls
2020-05-14 10:33:57 -07:00
..
achronix
Get rid of dffsr2dff.
2020-04-15 16:22:37 +02:00
anlogic
Get rid of dffsr2dff.
2020-04-15 16:22:37 +02:00
common
Cleanup; reduce Module::derive() calls
2020-05-14 10:33:57 -07:00
coolrunner2
kernel: big fat patch to use more ID::*, otherwise ID(*)
2020-04-02 09:51:32 -07:00
easic
Update doc that "-retime" calls abc with "-dff -D 1"
2019-12-30 13:28:29 -08:00
ecp5
ecp5: latches_map.v if *not* -asyncprld
2020-05-14 10:33:57 -07:00
efinix
Get rid of dffsr2dff.
2020-04-15 16:22:37 +02:00
gowin
gowin,ecp5: remove generated files in make clean.
2020-04-24 23:26:39 +00:00
greenpak4
kernel: big fat patch to use more ID::*, otherwise ID(*)
2020-04-02 09:51:32 -07:00
ice40
xilinx/ice40/ecp5: zinit requires selected wires, so select them all
2020-05-14 10:33:56 -07:00
intel
Get rid of dffsr2dff.
2020-04-15 16:22:37 +02:00
intel_alm
synth_*: no need to explicitly read +/abc9_model.v
2020-05-14 10:33:56 -07:00
sf2
Get rid of dffsr2dff.
2020-04-15 16:22:37 +02:00
xilinx
xilinx: gate specify/attributes from iverilog
2020-05-14 10:33:57 -07:00
.gitignore
added .gitignore files
2013-01-05 11:19:11 +01:00
Powered by Gitea Version: 1.27.2 Page: 1193ms Template: 13ms
Auto
English
Bahasa Indonesia Deutsch English Español Français Gaeilge Italiano Latviešu Magyar nyelv Nederlands Polski Português de Portugal Português do Brasil Suomi Svenska Türkçe Čeština Ελληνικά Български Русский Українська فارسی മലയാളം 日本語 简体中文 繁體中文(台灣) 繁體中文(香港) 한국어
Licenses API