yosys/tests/arch at e6b078d156f8690ab06d342da9be9af02cbcc3aa - yosys - Gitea: Git with a cup of tea

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gatecat 34a08750fa intel_alm: Fix illegal carry chains

Signed-off-by: gatecat <[email protected]>

2021-05-15 22:37:06 +01:00

..

tests: Centralize test collection and Makefile generation

2020-09-21 15:07:02 +02:00

intel_alm: Add multiply signedness to cells

2020-08-26 22:50:16 +02:00

Blackbox all whiteboxes after synthesis

2021-03-17 21:07:20 +00:00

tests: Centralize test collection and Makefile generation

2020-09-21 15:07:02 +02:00

tests: Centralize test collection and Makefile generation

2020-09-21 15:07:02 +02:00

tests: Centralize test collection and Makefile generation

2020-09-21 15:07:02 +02:00

intel_alm: Fix illegal carry chains

2021-05-15 22:37:06 +01:00

machxo2: Switch to LUT4 sim model which propagates less undefined/don't care values.

2021-02-23 17:39:58 +01:00

nexus: DSP inference support

2020-11-20 08:45:55 +00:00

quicklogic: ABC9 synthesis

2021-04-17 20:54:58 +02:00

ast: Use better parameter serialization for paramod names.

2021-03-18 00:52:00 +01:00

run-test.sh

Add default assignments to SB_LUT4

2021-04-20 12:46:21 +02:00