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luke
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yosys
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https://github.com/YosysHQ/yosys.git
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e6b078d156f8690ab06d342da9be9af02cbcc3aa
yosys
/
passes
T
History
Marcelina Kościelnicka
e6b078d156
opt_mem: Add reset/init value support.
2021-05-25 20:06:00 +02:00
..
cmds
kernel/rtlil: Extract some helpers for checking memory cell types.
2021-05-22 21:43:00 +02:00
equiv
equiv: Suggest running async2sync or clk2fflogic where appropriate.
2021-03-30 18:20:21 +02:00
fsm
…
hierarchy
…
memory
memory_bram: Respect write port priority.
2021-05-25 16:28:33 +02:00
opt
opt_mem: Add reset/init value support.
2021-05-25 20:06:00 +02:00
pmgen
Add _pm.h files to GENLIST, fixes vcxsrc target
2021-03-11 15:56:32 +01:00
proc
proc_arst: Add special-casing of clock signal in conditionals.
2021-03-15 17:17:29 +01:00
sat
sim: Add wide port support.
2021-05-25 02:57:32 +02:00
techmap
kernel/rtlil: Extract some helpers for checking memory cell types.
2021-05-22 21:43:00 +02:00
tests
…