mirror of https://github.com/YosysHQ/yosys.git
43 lines
844 B
Plaintext
43 lines
844 B
Plaintext
Clock gating
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need to determine when the D == Q
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Make sure that the flip flop has a clock but not ce: !ff.has_ce && ff.has_clk
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check if
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USE sat to determine when the Q is the same as D
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Q is the feedback, and then there's also the D which does in and select for the mux
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becomes the enable
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D = f(Q, other_inputs)
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!(D ^ f(Q, other_inputs))
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Look somewhat like this:
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Q is always going to be D
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But D itself has an enable built into it
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So what D really is is:
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Mux (D_r, Q, en) where en is the enable signal
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Our goal is to find en
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Equation:
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Q_next = (en ∧ D_r) ∨ (¬en ∧ Q)
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Equality question:
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!((Q_next) ^ ((en ∧ D_r) ∨ (¬en ∧ Q)))
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Universal Quantization
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FA(Q_next, D_r, Q) !((Q_next) ^ ((en ∧ D_r) ∨ (¬en ∧ Q)))
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SAT Equation
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FA(Q_next, D_r, Q) !((Q_next) ^ ((en ∧ D_r) ∨ (¬en ∧ Q)))
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