This website requires JavaScript.
Explore
Help
Sign In
luke
/
yosys
Watch
1
Star
0
Fork
0
mirror of
https://github.com/YosysHQ/yosys.git
synced
2026-09-05 03:32:09 +02:00
Code
Issues
Packages
Projects
Releases
Wiki
Activity
Files
e4a4c0e10c39edeffcae19f2635feea4ea0300df
yosys
/
techlibs
/
ice40
T
History
Tim Ansell
3cc31f197c
Fix spelling in -vpr help for synth_ice40
2017-12-08 18:44:45 -08:00
..
tests
…
.gitignore
…
arith_map.v
…
brams_init.py
…
brams_map.v
…
brams.txt
…
cells_map.v
Add "synth_ice40 -vpr"
2017-11-16 21:37:02 +01:00
cells_sim.v
Add remaining UltraPlus cells to ice40 techlib
2017-11-28 11:07:49 +00:00
ice40_ffinit.cc
Minor fixes in ice40_ff* passes for sloppy SB_DFF instantiations
2016-07-08 14:41:36 +02:00
ice40_ffssr.cc
Minor fixes in ice40_ff* passes for sloppy SB_DFF instantiations
2016-07-08 14:41:36 +02:00
ice40_opt.cc
…
latches_map.v
Added synth_ice40 support for latches via logic loops
2016-05-06 23:02:37 +02:00
Makefile.inc
Added synth_ice40 support for latches via logic loops
2016-05-06 23:02:37 +02:00
synth_ice40.cc
Fix spelling in -vpr help for synth_ice40
2017-12-08 18:44:45 -08:00
