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mirror of https://github.com/YosysHQ/yosys.git synced 2026-09-04 19:31:00 +02:00
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e4a4c0e10c39edeffcae19f2635feea4ea0300df
yosys/frontends
T
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Clifford Wolf e4a4c0e10c Add Verific OPER_SVA_STABLE support
2017-12-10 00:59:44 +01:00
..
ast
Fix error handling for nested always/initial
2017-12-02 18:52:05 +01:00
blif
Increase maximum LUT size in blifparse to 12 bits
2017-09-27 15:27:42 +02:00
ilang
Added avail params to ilang format, check module params in 'hierarchy -check'
2016-10-22 11:05:49 +02:00
json
Parse reals as string in JSON front-end
2017-09-26 14:37:03 +02:00
liberty
Added liberty parser support for types within cell decls
2016-09-23 13:53:23 +02:00
verific
Add Verific OPER_SVA_STABLE support
2017-12-10 00:59:44 +01:00
verilog
Add Verilog "automatic" keyword (ignored in synthesis)
2017-11-23 08:51:38 +01:00
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