mirror of
https://github.com/YosysHQ/yosys.git
synced 2026-10-06 10:03:36 +02:00
George Rennie
e44fcbe19c
* this was added earlier in the PR with the intention of making equiv_opt work, but it means barriers are lost through passes like aigmap and can potentially be used in optimization passes so it is better to remove it
530 lines
14 KiB
C++
530 lines
14 KiB
C++
/*
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* yosys -- Yosys Open SYnthesis Suite
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*
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* Copyright (C) 2012 Claire Xenia Wolf <[email protected]>
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*
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* Permission to use, copy, modify, and/or distribute this software for any
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* purpose with or without fee is hereby granted, provided that the above
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* copyright notice and this permission notice appear in all copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*
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*/
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#include "kernel/cellaigs.h"
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YOSYS_NAMESPACE_BEGIN
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AigNode::AigNode()
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{
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portbit = -1;
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inverter = false;
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left_parent = -1;
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right_parent = -1;
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}
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bool AigNode::operator==(const AigNode &other) const
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{
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if (portname != other.portname) return false;
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if (portbit != other.portbit) return false;
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if (inverter != other.inverter) return false;
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if (left_parent != other.left_parent) return false;
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if (right_parent != other.right_parent) return false;
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return true;
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}
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Hasher AigNode::hash_into(Hasher h) const
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{
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h.eat(portname);
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h.eat(portbit);
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h.eat(inverter);
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h.eat(left_parent);
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h.eat(right_parent);
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return h;
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}
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bool Aig::operator==(const Aig &other) const
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{
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return name == other.name;
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}
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Hasher Aig::hash_into(Hasher h) const
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{
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h.eat(name);
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return h;
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}
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struct AigMaker
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{
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Aig *aig;
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Cell *cell;
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idict<AigNode> aig_indices;
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AigMaker(Aig *aig, Cell *cell) : aig(aig), cell(cell) {}
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int node2index(const AigNode &node)
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{
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if (node.left_parent > node.right_parent) {
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AigNode n(node);
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std::swap(n.left_parent, n.right_parent);
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return node2index(n);
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}
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if (!aig_indices.count(node)) {
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aig_indices.expect(node, GetSize(aig->nodes));
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aig->nodes.push_back(node);
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}
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return aig_indices.at(node);
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}
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int bool_node(bool value)
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{
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AigNode node;
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node.inverter = value;
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return node2index(node);
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}
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int inport(IdString portname, int portbit = 0, bool inverter = false)
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{
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if (portbit >= GetSize(cell->getPort(portname))) {
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if (cell->parameters.count(portname.str() + "_SIGNED") && cell->getParam(portname.str() + "_SIGNED").as_bool())
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return inport(portname, GetSize(cell->getPort(portname))-1, inverter);
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return bool_node(inverter);
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}
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AigNode node;
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node.portname = portname;
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node.portbit = portbit;
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node.inverter = inverter;
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return node2index(node);
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}
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vector<int> inport_vec(IdString portname, int width)
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{
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vector<int> vec;
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for (int i = 0; i < width; i++)
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vec.push_back(inport(portname, i));
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return vec;
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}
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int not_inport(IdString portname, int portbit = 0)
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{
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return inport(portname, portbit, true);
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}
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int not_gate(int A)
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{
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AigNode node(aig_indices[A]);
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node.outports.clear();
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node.inverter = !node.inverter;
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return node2index(node);
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}
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int and_gate(int A, int B, bool inverter = false)
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{
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if (A == B)
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return inverter ? not_gate(A) : A;
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const AigNode &nA = aig_indices[A];
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const AigNode &nB = aig_indices[B];
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AigNode nB_inv(nB);
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nB_inv.inverter = !nB_inv.inverter;
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if (nA == nB_inv)
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return bool_node(inverter);
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bool nA_bool = nA.portbit < 0 && nA.left_parent < 0 && nA.right_parent < 0;
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bool nB_bool = nB.portbit < 0 && nB.left_parent < 0 && nB.right_parent < 0;
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if (nA_bool && nB_bool) {
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bool bA = nA.inverter;
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bool bB = nB.inverter;
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return bool_node(inverter != (bA && bB));
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}
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if (nA_bool) {
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bool bA = nA.inverter;
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if (inverter)
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return bA ? not_gate(B) : bool_node(true);
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return bA ? B : bool_node(false);
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}
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if (nB_bool) {
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bool bB = nB.inverter;
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if (inverter)
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return bB ? not_gate(A) : bool_node(true);
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return bB ? A : bool_node(false);
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}
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AigNode node;
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node.inverter = inverter;
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node.left_parent = A;
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node.right_parent = B;
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return node2index(node);
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}
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int nand_gate(int A, int B)
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{
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return and_gate(A, B, true);
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}
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int or_gate(int A, int B)
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{
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int not_a = not_gate(A);
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int not_b = not_gate(B);
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return nand_gate(not_a, not_b);
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}
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int nor_gate(int A, int B)
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{
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int not_a = not_gate(A);
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int not_b = not_gate(B);
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return and_gate(not_a, not_b);
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}
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int xor_gate(int A, int B)
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{
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int a_and_b = and_gate(A, B);
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int a_nor_b = nor_gate(A, B);
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return nor_gate(a_and_b, a_nor_b);
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}
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int xnor_gate(int A, int B)
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{
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int a_and_b = and_gate(A, B);
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int a_nor_b = nor_gate(A, B);
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return or_gate(a_and_b, a_nor_b);
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}
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int andnot_gate(int A, int B)
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{
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int not_b = not_gate(B);
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return and_gate(A, not_b);
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}
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int ornot_gate(int A, int B)
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{
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int not_b = not_gate(B);
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return or_gate(A, not_b);
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}
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int mux_gate(int A, int B, int S)
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{
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int not_s = not_gate(S);
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int a_active = and_gate(A, not_s);
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int b_active = and_gate(B, S);
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return or_gate(a_active, b_active);
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}
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vector<int> adder(const vector<int> &A, const vector<int> &B, int carry_in, vector<int> *X = nullptr, vector<int> *CO = nullptr)
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{
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vector<int> Y(GetSize(A));
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log_assert(GetSize(A) == GetSize(B));
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for (int i = 0; i < GetSize(A); i++) {
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int a_xor_b = xor_gate(A[i], B[i]);
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int a_or_b = or_gate(A[i], B[i]);
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int a_and_b = and_gate(A[i], B[i]);
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Y[i] = xor_gate(a_xor_b, carry_in);
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int tmp = and_gate(a_or_b, carry_in);
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int carry_out = or_gate(a_and_b, tmp);
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if (X != nullptr)
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X->at(i) = a_xor_b;
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if (CO != nullptr)
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CO->at(i) = carry_out;
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carry_in = carry_out;
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}
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return Y;
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}
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void outport(int node, IdString portname, int portbit = 0)
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{
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if (portbit < GetSize(cell->getPort(portname)))
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aig->nodes.at(node).outports.push_back(pair<IdString, int>(portname, portbit));
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}
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void outport_bool(int node, IdString portname)
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{
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outport(node, portname);
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for (int i = 1; i < GetSize(cell->getPort(portname)); i++)
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outport(bool_node(false), portname, i);
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}
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void outport_vec(const vector<int> &vec, IdString portname)
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{
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for (int i = 0; i < GetSize(vec); i++)
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outport(vec.at(i), portname, i);
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}
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};
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Aig::Aig(Cell *cell)
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{
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if (cell->type[0] != '$')
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return;
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AigMaker mk(this, cell);
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name = cell->type.str();
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string mkname_last;
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bool mkname_a_signed = false;
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bool mkname_b_signed = false;
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bool mkname_is_signed = false;
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cell->parameters.sort();
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for (auto p : cell->parameters)
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{
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if (p.first == ID::A_WIDTH && mkname_a_signed) {
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name = mkname_last + stringf(":%d%c", p.second.as_int(), mkname_is_signed ? 'S' : 'U');
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} else if (p.first == ID::B_WIDTH && mkname_b_signed) {
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name = mkname_last + stringf(":%d%c", p.second.as_int(), mkname_is_signed ? 'S' : 'U');
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} else {
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mkname_last = name;
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name += stringf(":%d", p.second.as_int());
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}
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mkname_a_signed = false;
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mkname_b_signed = false;
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mkname_is_signed = false;
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if (p.first == ID::A_SIGNED) {
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mkname_a_signed = true;
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mkname_is_signed = p.second.as_bool();
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}
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if (p.first == ID::B_SIGNED) {
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mkname_b_signed = true;
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mkname_is_signed = p.second.as_bool();
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}
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}
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if (cell->type.in(ID($not), ID($_NOT_), ID($pos), ID($buf), ID($_BUF_)))
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{
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for (int i = 0; i < GetSize(cell->getPort(ID::Y)); i++) {
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int A = mk.inport(ID::A, i);
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int Y = cell->type.in(ID($not), ID($_NOT_)) ? mk.not_gate(A) : A;
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mk.outport(Y, ID::Y, i);
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}
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goto optimize;
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}
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if (cell->type.in(ID($and), ID($_AND_), ID($_NAND_), ID($or), ID($_OR_), ID($_NOR_), ID($xor), ID($xnor), ID($_XOR_), ID($_XNOR_), ID($_ANDNOT_), ID($_ORNOT_)))
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{
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for (int i = 0; i < GetSize(cell->getPort(ID::Y)); i++) {
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int A = mk.inport(ID::A, i);
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int B = mk.inport(ID::B, i);
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int Y = cell->type.in(ID($and), ID($_AND_)) ? mk.and_gate(A, B) :
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cell->type.in(ID($_NAND_)) ? mk.nand_gate(A, B) :
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cell->type.in(ID($or), ID($_OR_)) ? mk.or_gate(A, B) :
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cell->type.in(ID($_NOR_)) ? mk.nor_gate(A, B) :
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cell->type.in(ID($xor), ID($_XOR_)) ? mk.xor_gate(A, B) :
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cell->type.in(ID($xnor), ID($_XNOR_)) ? mk.xnor_gate(A, B) :
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cell->type.in(ID($_ANDNOT_)) ? mk.andnot_gate(A, B) :
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cell->type.in(ID($_ORNOT_)) ? mk.ornot_gate(A, B) : -1;
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mk.outport(Y, ID::Y, i);
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}
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goto optimize;
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}
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if (cell->type.in(ID($mux), ID($_MUX_), ID($_NMUX_)))
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{
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int S = mk.inport(ID::S);
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for (int i = 0; i < GetSize(cell->getPort(ID::Y)); i++) {
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int A = mk.inport(ID::A, i);
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int B = mk.inport(ID::B, i);
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int Y = mk.mux_gate(A, B, S);
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if (cell->type == ID($_NMUX_))
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Y = mk.not_gate(Y);
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mk.outport(Y, ID::Y, i);
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}
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goto optimize;
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}
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if (cell->type.in(ID($reduce_and), ID($reduce_or), ID($reduce_xor), ID($reduce_xnor), ID($reduce_bool)))
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{
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int Y = mk.inport(ID::A, 0);
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for (int i = 1; i < GetSize(cell->getPort(ID::A)); i++) {
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int A = mk.inport(ID::A, i);
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if (cell->type == ID($reduce_and)) Y = mk.and_gate(A, Y);
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if (cell->type == ID($reduce_or)) Y = mk.or_gate(A, Y);
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if (cell->type == ID($reduce_bool)) Y = mk.or_gate(A, Y);
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if (cell->type == ID($reduce_xor)) Y = mk.xor_gate(A, Y);
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if (cell->type == ID($reduce_xnor)) Y = mk.xor_gate(A, Y);
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}
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if (cell->type == ID($reduce_xnor))
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Y = mk.not_gate(Y);
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mk.outport(Y, ID::Y, 0);
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for (int i = 1; i < GetSize(cell->getPort(ID::Y)); i++)
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mk.outport(mk.bool_node(false), ID::Y, i);
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goto optimize;
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}
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if (cell->type.in(ID($logic_not), ID($logic_and), ID($logic_or)))
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{
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int A = mk.inport(ID::A, 0), Y = -1;
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for (int i = 1; i < GetSize(cell->getPort(ID::A)); i++)
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A = mk.or_gate(mk.inport(ID::A, i), A);
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if (cell->type.in(ID($logic_and), ID($logic_or))) {
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int B = mk.inport(ID::B, 0);
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for (int i = 1; i < GetSize(cell->getPort(ID::B)); i++)
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B = mk.or_gate(mk.inport(ID::B, i), B);
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if (cell->type == ID($logic_and)) Y = mk.and_gate(A, B);
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if (cell->type == ID($logic_or)) Y = mk.or_gate(A, B);
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} else {
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if (cell->type == ID($logic_not)) Y = mk.not_gate(A);
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}
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mk.outport_bool(Y, ID::Y);
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goto optimize;
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}
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if (cell->type.in(ID($add), ID($sub)))
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{
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int width = GetSize(cell->getPort(ID::Y));
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vector<int> A = mk.inport_vec(ID::A, width);
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vector<int> B = mk.inport_vec(ID::B, width);
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int carry = mk.bool_node(false);
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if (cell->type == ID($sub)) {
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for (auto &n : B)
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n = mk.not_gate(n);
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carry = mk.not_gate(carry);
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}
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vector<int> Y = mk.adder(A, B, carry);
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mk.outport_vec(Y, ID::Y);
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goto optimize;
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}
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if (cell->type.in(ID($lt), ID($gt), ID($le), ID($ge)))
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{
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int width = std::max(GetSize(cell->getPort(ID::A)),
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GetSize(cell->getPort(ID::B))) + 1;
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vector<int> A = mk.inport_vec(ID::A, width);
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vector<int> B = mk.inport_vec(ID::B, width);
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if (cell->type.in(ID($gt), ID($ge)))
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std::swap(A, B);
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int carry = mk.bool_node(!cell->type.in(ID($le), ID($ge)));
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for (auto &n : B)
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n = mk.not_gate(n);
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vector<int> Y = mk.adder(A, B, carry);
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mk.outport(Y.back(), ID::Y);
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for (int i = 1; i < GetSize(cell->getPort(ID::Y)); i++)
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mk.outport(mk.bool_node(false), ID::Y, i);
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goto optimize;
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}
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if (cell->type == ID($alu))
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{
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int width = GetSize(cell->getPort(ID::Y));
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vector<int> A = mk.inport_vec(ID::A, width);
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vector<int> B = mk.inport_vec(ID::B, width);
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int carry = mk.inport(ID::CI);
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int binv = mk.inport(ID::BI);
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for (auto &n : B)
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n = mk.xor_gate(n, binv);
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vector<int> X(width), CO(width);
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vector<int> Y = mk.adder(A, B, carry, &X, &CO);
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for (int i = 0; i < width; i++)
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X[i] = mk.xor_gate(A[i], B[i]);
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mk.outport_vec(Y, ID::Y);
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mk.outport_vec(X, ID::X);
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mk.outport_vec(CO, ID::CO);
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goto optimize;
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}
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if (cell->type.in(ID($eq), ID($ne)))
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{
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int width = max(GetSize(cell->getPort(ID::A)), GetSize(cell->getPort(ID::B)));
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vector<int> A = mk.inport_vec(ID::A, width);
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vector<int> B = mk.inport_vec(ID::B, width);
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int Y = mk.bool_node(false);
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for (int i = 0; i < width; i++)
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Y = mk.or_gate(Y, mk.xor_gate(A[i], B[i]));
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if (cell->type == ID($eq))
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Y = mk.not_gate(Y);
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mk.outport_bool(Y, ID::Y);
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goto optimize;
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}
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if (cell->type == ID($_AOI3_))
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{
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int A = mk.inport(ID::A);
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int B = mk.inport(ID::B);
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int C = mk.inport(ID::C);
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int Y = mk.nor_gate(mk.and_gate(A, B), C);
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mk.outport(Y, ID::Y);
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goto optimize;
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}
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|
if (cell->type == ID($_OAI3_))
|
|
{
|
|
int A = mk.inport(ID::A);
|
|
int B = mk.inport(ID::B);
|
|
int C = mk.inport(ID::C);
|
|
int Y = mk.nand_gate(mk.or_gate(A, B), C);
|
|
mk.outport(Y, ID::Y);
|
|
goto optimize;
|
|
}
|
|
|
|
if (cell->type == ID($_AOI4_))
|
|
{
|
|
int A = mk.inport(ID::A);
|
|
int B = mk.inport(ID::B);
|
|
int C = mk.inport(ID::C);
|
|
int D = mk.inport(ID::D);
|
|
int a_and_b = mk.and_gate(A, B);
|
|
int Y = mk.nor_gate(a_and_b, mk.and_gate(C, D));
|
|
mk.outport(Y, ID::Y);
|
|
goto optimize;
|
|
}
|
|
|
|
if (cell->type == ID($_OAI4_))
|
|
{
|
|
int A = mk.inport(ID::A);
|
|
int B = mk.inport(ID::B);
|
|
int C = mk.inport(ID::C);
|
|
int D = mk.inport(ID::D);
|
|
int a_or_b = mk.or_gate(A, B);
|
|
int Y = mk.nand_gate(a_or_b, mk.or_gate(C, D));
|
|
mk.outport(Y, ID::Y);
|
|
goto optimize;
|
|
}
|
|
|
|
name.clear();
|
|
return;
|
|
|
|
optimize:;
|
|
pool<int> used_old_ids;
|
|
vector<AigNode> new_nodes;
|
|
dict<int, int> old_to_new_ids;
|
|
old_to_new_ids[-1] = -1;
|
|
|
|
for (int i = GetSize(nodes)-1; i >= 0; i--) {
|
|
if (!nodes[i].outports.empty())
|
|
used_old_ids.insert(i);
|
|
if (!used_old_ids.count(i))
|
|
continue;
|
|
if (nodes[i].left_parent >= 0)
|
|
used_old_ids.insert(nodes[i].left_parent);
|
|
if (nodes[i].right_parent >= 0)
|
|
used_old_ids.insert(nodes[i].right_parent);
|
|
}
|
|
|
|
for (int i = 0; i < GetSize(nodes); i++) {
|
|
if (!used_old_ids.count(i))
|
|
continue;
|
|
nodes[i].left_parent = old_to_new_ids.at(nodes[i].left_parent);
|
|
nodes[i].right_parent = old_to_new_ids.at(nodes[i].right_parent);
|
|
old_to_new_ids[i] = GetSize(new_nodes);
|
|
new_nodes.push_back(nodes[i]);
|
|
}
|
|
|
|
new_nodes.swap(nodes);
|
|
}
|
|
|
|
YOSYS_NAMESPACE_END
|