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mirror of https://github.com/YosysHQ/yosys.git synced 2026-08-31 18:24:48 +02:00
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e3c4791e5ba446e484385be7385fca2a4cfa87d6
yosys/techlibs/microchip
T
History
chunlin min e3c4791e5b move microchip tests from techlibs/microchip/tests to tests/arch/microchip
2024-07-04 14:16:52 -04:00
..
arith_map.v
changes made to filenames + references
2024-07-04 08:53:41 -07:00
brams_defs.vh
changes made to filenames + references
2024-07-04 08:53:41 -07:00
cells_map.v
changes made to filenames + references
2024-07-04 08:53:41 -07:00
cells_sim.v
use output reg instead of additional reg declaration
2024-07-04 14:13:26 -04:00
LSRAM_map.v
changes made to filenames + references
2024-07-04 08:53:41 -07:00
LSRAM.txt
changes made to filenames + references
2024-07-04 08:53:41 -07:00
Makefile.inc
fixed typos, build with makefile succeeds
2024-07-04 09:33:58 -07:00
microchip_dffopt.cc
changes made to filenames + references
2024-07-04 08:53:41 -07:00
polarfire_dsp_map.v
changes made to filenames + references
2024-07-04 08:53:41 -07:00
synth_microchip.cc
missed a few pf instances
2024-07-04 10:25:15 -07:00
uSRAM_map.v
changes made to filenames + references
2024-07-04 08:53:41 -07:00
uSRAM.txt
changes made to filenames + references
2024-07-04 08:53:41 -07:00
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