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mirror of https://github.com/YosysHQ/yosys.git synced 2026-10-07 18:43:22 +02:00
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e340532ce5d60129fbfb2e1b0a3eb916ec856b26
yosys/tests
T
History
Clifford Wolf c5e26f839c Added additional mem2reg testcase
2013-11-18 19:55:39 +01:00
..
asicworld
Fixed undef behavior in tests/asicworld/code_verilog_tutorial_fsm_full_tb.v
2013-05-24 15:15:59 +02:00
hana
added more .gitignore files (make test)
2013-01-05 11:35:52 +01:00
i2c_bench
Moved common techlib files to techlibs/common
2013-09-15 11:52:57 +02:00
k68_vltor
Now only use value from "initial" when no matching "always" block is found
2013-03-31 11:51:12 +02:00
no-icarus
initial import
2013-01-05 11:13:26 +01:00
simple
Added additional mem2reg testcase
2013-11-18 19:55:39 +01:00
tools
Moved common techlib files to techlibs/common
2013-09-15 11:52:57 +02:00
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