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mirror of https://github.com/YosysHQ/yosys.git synced 2026-10-08 02:52:53 +02:00
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e340532ce5d60129fbfb2e1b0a3eb916ec856b26
yosys/frontends
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Clifford Wolf e340532ce5 Added init= attribute for fpga-style reset values
2013-11-20 01:49:37 +01:00
..
ast
Fixed two bugs in mem2reg functionality in AST frontend
2013-11-18 19:55:12 +01:00
ilang
Fixed parsing of value-less attributes in ilang
2013-10-23 18:38:31 +02:00
verilog
Added init= attribute for fpga-style reset values
2013-11-20 01:49:37 +01:00
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