This website requires JavaScript.
Explore
Help
Sign In
luke
/
yosys
Watch
1
Star
0
Fork
0
mirror of
https://github.com/YosysHQ/yosys.git
synced
2026-08-31 18:24:48 +02:00
Code
Issues
Packages
Projects
Releases
Wiki
Activity
Files
e2e7065590ff8dbd1baa7bbfd9c91fb890428f55
yosys
/
techlibs
/
quicklogic
/
common
T
History
N. Engelhardt
98769010af
synth_quicklogic: rearrange files to prepare for adding more architectures
2023-12-04 15:52:02 +01:00
..
cells_sim.v
synth_quicklogic: rearrange files to prepare for adding more architectures
2023-12-04 15:52:02 +01:00