mirror of https://github.com/YosysHQ/yosys.git
14 lines
304 B
Verilog
14 lines
304 B
Verilog
module bottom(input clk, input wire [1:0] i, output reg [1:0] q);
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reg [1:0] q1;
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always @(posedge clk) begin
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q1 <= i;
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q <= q1;
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end
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endmodule
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module top(input clk, input wire [1:0] i, output reg [1:0] q);
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reg [1:0] q1;
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bottom u1 (.clk(clk), .i(i), .q(q1));
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not u2 (q, q1);
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endmodule
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