mirror of https://github.com/YosysHQ/yosys.git
189 lines
3.7 KiB
Plaintext
189 lines
3.7 KiB
Plaintext
log -header "Simple positive case"
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log -push
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design -reset
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read_verilog <<EOF
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module top(a, b, s, y);
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input wire signed [7:0] a;
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input wire signed [7:0] b;
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input wire s;
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output wire signed [7:0] y;
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assign y = -(s ? a : b);
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endmodule
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EOF
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proc; opt
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check -assert
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equiv_opt -assert negopt -pre
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design -load postopt
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select -assert-count 1 t:$mux
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select -assert-count 2 t:$neg
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design -reset
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log -pop
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log -header "With intermediate signal"
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log -push
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design -reset
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read_verilog <<EOF
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module top(a, b, s, y);
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input wire signed [7:0] a;
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input wire signed [7:0] b;
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input wire s;
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output wire signed [7:0] y;
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wire signed [7:0] m;
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assign m = s ? a : b;
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assign y = -m;
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endmodule
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EOF
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proc; opt
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check -assert
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equiv_opt -assert negopt -pre
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design -load postopt
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select -assert-count 1 t:$mux
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select -assert-count 2 t:$neg
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design -reset
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log -pop
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log -header "Positive case: neg input is sign extension of mux output"
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log -push
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design -reset
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read_verilog <<EOF
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module top(a, b, s, y);
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input wire signed [7:0] a;
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input wire signed [7:0] b;
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input wire s;
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output wire signed [11:0] y;
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wire signed [7:0] m;
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wire signed [11:0] m_ext;
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assign m = s ? a : b;
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assign m_ext = m;
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assign y = -m_ext;
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endmodule
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EOF
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proc; opt
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check -assert
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equiv_opt -assert negopt -pre
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design -load postopt
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select -assert-count 1 t:$mux
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select -assert-count 2 t:$neg
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design -reset
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log -pop
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log -header "Positive case: neg input is zero extension of mux output"
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log -push
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design -reset
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read_verilog <<EOF
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module top(a, b, s, y);
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input wire [7:0] a;
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input wire [7:0] b;
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input wire s;
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output wire [11:0] y;
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wire [7:0] m;
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wire [11:0] m_ext;
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assign m = s ? a : b;
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assign m_ext = m;
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assign y = -m_ext;
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endmodule
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EOF
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proc; opt
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check -assert
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equiv_opt -assert negopt -pre
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design -load postopt
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select -assert-count 1 t:$mux
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select -assert-count 2 t:$neg
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design -reset
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log -pop
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log -header "Negative case: mux output has extra fanout"
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log -push
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design -reset
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read_verilog <<EOF
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module top(a, b, s, y, z);
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input wire signed [7:0] a;
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input wire signed [7:0] b;
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input wire s;
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output wire signed [7:0] y;
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output wire signed [7:0] z;
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(* keep *) wire signed [7:0] m;
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assign m = s ? a : b;
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assign y = -m;
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assign z = m;
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endmodule
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EOF
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proc; opt
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check -assert
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equiv_opt -assert negopt -pre
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design -load postopt
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# Should NOT transform due to extra fanout on mux output
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select -assert-count 1 t:$mux
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select -assert-count 1 t:$neg
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design -reset
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log -pop
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log -header "Anchor case: mux inputs narrower than neg output"
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log -push
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design -reset
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read_verilog <<EOF
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module top(a, b, s, y);
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input wire signed [3:0] a;
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input wire signed [3:0] b;
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input wire s;
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output wire signed [7:0] y;
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wire signed [3:0] m;
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assign m = s ? a : b;
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assign y = -m;
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endmodule
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EOF
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proc; opt
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check -assert
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equiv_opt -assert negopt -pre
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design -load postopt
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select -assert-count 1 t:$mux
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select -assert-count 2 t:$neg
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design -reset
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log -pop
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log -header "Negative case: signedness mismatch on mux output"
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log -push
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design -reset
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read_verilog <<EOF
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module top(a, b, s, y);
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input wire signed [7:0] a;
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input wire [7:0] b;
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input wire s;
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output wire signed [7:0] y;
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wire [7:0] m;
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assign m = s ? a : b;
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assign y = -m;
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endmodule
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EOF
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proc; opt
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check -assert
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equiv_opt -assert negopt -pre
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design -load postopt
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select -assert-count 1 t:$mux
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select -assert-none t:$sub
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design -reset
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log -pop
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log -header "Negative case: neg input not from mux output"
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log -push
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design -reset
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read_verilog <<EOF
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module top(a, b, s, y);
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input wire signed [7:0] a;
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input wire signed [7:0] b;
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input wire s;
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output wire signed [7:0] y;
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wire signed [7:0] m;
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assign m = s ? a : b;
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assign y = -(m ^ 8'h00);
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endmodule
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EOF
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proc; opt
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check -assert
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equiv_opt -assert negopt -pre
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design -load postopt
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select -assert-count 1 t:$mux
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select -assert-none t:$sub
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design -reset
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log -pop
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