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e18aeda7ed3b3dbf4700e25c2bc745c93541b3b8
yosys/techlibs
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Eddie Hung e18aeda7ed Fix $lut input ordering -- SigSpec(std::initializer_list<>) is backwards
Just like Verilog...
2020-01-27 14:02:13 -08:00
..
achronix
Update doc that "-retime" calls abc with "-dff -D 1"
2019-12-30 13:28:29 -08:00
anlogic
Merge pull request #1604 from whitequark/unify-ram-naming
2020-01-02 21:06:17 +00:00
common
Do not map $eq and $ne in cmp2lut, only proper arithmetic cmp
2019-11-11 15:07:29 +01:00
coolrunner2
Update doc that "-retime" calls abc with "-dff -D 1"
2019-12-30 13:28:29 -08:00
easic
Update doc that "-retime" calls abc with "-dff -D 1"
2019-12-30 13:28:29 -08:00
ecp5
xilinx/ice40/ecp5: undo permuting LUT masks in lut_map
2020-01-27 13:30:27 -08:00
efinix
Merge pull request #1604 from whitequark/unify-ram-naming
2020-01-02 21:06:17 +00:00
gowin
Merge pull request #1604 from whitequark/unify-ram-naming
2020-01-02 21:06:17 +00:00
greenpak4
Update doc that "-retime" calls abc with "-dff -D 1"
2019-12-30 13:28:29 -08:00
ice40
Fix $lut input ordering -- SigSpec(std::initializer_list<>) is backwards
2020-01-27 14:02:13 -08:00
intel
Merge pull request #1604 from whitequark/unify-ram-naming
2020-01-02 21:06:17 +00:00
sf2
Update doc that "-retime" calls abc with "-dff -D 1"
2019-12-30 13:28:29 -08:00
xilinx
xilinx/ice40/ecp5: undo permuting LUT masks in lut_map
2020-01-27 13:30:27 -08:00
.gitignore
added .gitignore files
2013-01-05 11:19:11 +01:00
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