yosys/passes
Krystine Sherwin e188142aeb memory_libmap: Add -force-params
Reduce complexity for adi brams by unconditionally providing the WIDTH and ABITS parameters.
2026-01-05 07:56:00 +00:00
..
cmds Merge pull request #5571 from YosysHQ/micko/warning 2025-12-23 16:32:10 +01:00
equiv Merge pull request #5357 from rocallahan/builtin-ff 2025-09-17 11:37:16 +02:00
fsm fsm_detect: add adff detection 2025-11-06 23:29:47 +02:00
hierarchy hierarchy.cc: Tidying 2025-10-15 09:42:47 +13:00
memory memory_libmap: Add -force-params 2026-01-05 07:56:00 +00:00
opt avoid merging formal properties 2025-12-17 20:25:24 +01:00
pmgen Remove .c_str() from log_cmd_error() and log_file_error() parameters 2025-09-16 22:59:08 +00:00
proc Update passes/proc to avoid bits() 2025-09-16 03:17:23 +00:00
sat Revert sim's cycle_width default back to 10, but keep -width option 2025-10-20 14:40:05 +02:00
techmap Merge pull request #5568 from rocallahan/abc-spawn-errno 2025-12-23 08:09:14 +01:00
tests test_cell.cc: Generate .aag for all compatible cells 2025-12-02 14:03:36 +13:00