Clifford Wolf 0fc6e2bfcf Merge pull request #770 from whitequark/opt_expr_cmp ... opt_expr: refactor and improve simplification of comparisons		2019-01-02 17:34:04 +01:00
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asicworld	…
bram	…
errors	Rename the generic "Syntax error" message from the Verilog/SystemVerilog parser into unique,	2018-10-25 02:37:56 +03:00
fsm	…
hana	…
lut	cmp2lut: new techmap pass.	2019-01-02 07:53:31 +00:00
memories	…
opt	opt_expr: improve simplification of comparisons with large constants.	2019-01-02 15:45:28 +00:00
realmath	…
sat	Allow $size and $bits in verilog mode, actually check test case	2017-09-29 11:56:43 +02:00
share	…
simple	Basic test for checking correct synthesis of SystemVerilog interfaces	2018-10-18 22:40:53 +02:00
smv	…
sva	Squelch a little more trailing whitespace	2018-12-29 12:46:54 +01:00
svinterfaces	Add missing .gitignore	2018-12-06 07:29:37 +01:00
techmap	…
tools	Fixed typo (sikp -> skip)	2018-06-05 22:41:27 +03:00
unit	Build hotfix in tests/unit/Makefile	2016-12-11 10:58:49 +01:00
various	Modified errors into warnings	2018-06-05 18:03:22 +03:00
vloghtb	…