Clifford Wolf 0fc6e2bfcf Merge pull request #770 from whitequark/opt_expr_cmp ...

opt_expr: refactor and improve simplification of comparisons

2019-01-02 17:34:04 +01:00

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asicworld

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bram

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errors

Rename the generic "Syntax error" message from the Verilog/SystemVerilog parser into unique,

2018-10-25 02:37:56 +03:00

fsm

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hana

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lut

cmp2lut: new techmap pass.

2019-01-02 07:53:31 +00:00

memories

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opt

opt_expr: improve simplification of comparisons with large constants.

2019-01-02 15:45:28 +00:00

realmath

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sat

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share

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simple

Basic test for checking correct synthesis of SystemVerilog interfaces

2018-10-18 22:40:53 +02:00

smv

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sva

Squelch a little more trailing whitespace

2018-12-29 12:46:54 +01:00

svinterfaces

Add missing .gitignore

2018-12-06 07:29:37 +01:00

techmap

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tools

Fixed typo (sikp -> skip)

2018-06-05 22:41:27 +03:00

unit

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various

Modified errors into warnings

2018-06-05 18:03:22 +03:00

vloghtb

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