yosys/frontends/verilog
Dag Lem f09ea16bd1 Resolve struct member multiple dimensions defined in stages with typedef 2024-02-11 11:26:52 -05:00
..
.gitignore
Makefile.inc
const2ast.cc
preproc.cc set default_nettype to wire for resetall 2022-08-10 13:28:19 +02:00
preproc.h verilog: save and restore overwritten macro arguments 2021-07-28 21:52:16 -04:00
verilog_frontend.cc Optionally suppress output from display system tasks in read_verilog 2024-01-11 13:12:53 +01:00
verilog_frontend.h verilog: Squash a memory leak. 2021-06-14 17:07:41 +02:00
verilog_lexer.l fmt: %t/$time support 2023-08-11 04:46:52 +02:00
verilog_parser.y Resolve struct member multiple dimensions defined in stages with typedef 2024-02-11 11:26:52 -05:00