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mirror of https://github.com/YosysHQ/yosys.git synced 2026-08-30 09:58:22 +02:00
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dfbd7dd15a1520ce0c01d2722aaacbf7b7be71fa
yosys/techlibs/common
T
History
Clifford Wolf eb571cba6a Replaced $__alu CO/CS outputs with full-width CO output
2014-08-30 15:12:39 +02:00
..
adff2dff.v
Added adff2dff.v (for techmap -share_map)
2014-08-07 16:14:38 +02:00
blackbox.sed
Renamed stdcells_sim.v to simcells.v and fixed blackbox.v
2013-11-24 20:44:00 +01:00
Makefile.inc
Added adff2dff.v (for techmap -share_map)
2014-08-07 16:14:38 +02:00
pmux2mux.v
Added techlibs/common/pmux2mux.v
2014-01-17 20:06:15 +01:00
simcells.v
Added additional gate types: $_NAND_ $_NOR_ $_XNOR_ $_AOI3_ $_OAI3_ $_AOI4_ $_OAI4_
2014-08-16 18:29:39 +02:00
simlib.v
Renamed $lut ports to follow A-Y naming scheme
2014-08-15 14:18:40 +02:00
techmap.v
Replaced $__alu CO/CS outputs with full-width CO output
2014-08-30 15:12:39 +02:00
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