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mirror of https://github.com/YosysHQ/yosys.git synced 2026-09-08 12:44:23 +02:00
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df69febb1e8293d9234e1dc3b6be874cbb44fe3e
yosys/techlibs/anlogic
T
History
Eddie Hung 956ecd48f7 kernel: big fat patch to use more ID::*, otherwise ID(*)
2020-04-02 09:51:32 -07:00
..
anlogic_eqn.cc
kernel: big fat patch to use more ID::*, otherwise ID(*)
2020-04-02 09:51:32 -07:00
anlogic_fixcarry.cc
kernel: big fat patch to use more ID::*, otherwise ID(*)
2020-04-02 09:51:32 -07:00
arith_map.v
Fix missing newline at end of file
2019-08-22 18:09:37 +02:00
cells_map.v
Fix anlogic async flop mapping
2020-01-01 08:43:16 -08:00
cells_sim.v
make note that it is for latch mode
2019-09-18 17:48:16 +02:00
eagle_bb.v
Revert "Leave only real black box cells"
2018-12-17 23:20:40 +08:00
lutram_init_16x4.vh
Harmonize BRAM/LUTRAM descriptions across all of Yosys.
2020-01-01 12:30:00 +00:00
lutrams_map.v
Harmonize BRAM/LUTRAM descriptions across all of Yosys.
2020-01-01 12:30:00 +00:00
lutrams.txt
Harmonize BRAM/LUTRAM descriptions across all of Yosys.
2020-01-01 12:30:00 +00:00
Makefile.inc
Harmonize BRAM/LUTRAM descriptions across all of Yosys.
2020-01-01 12:30:00 +00:00
synth_anlogic.cc
synth_*: call 'opt -fast' after 'techmap'
2020-02-05 18:39:01 -08:00
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