luke/yosys
1
0
Fork 0
mirror of https://github.com/YosysHQ/yosys.git synced 2026-10-07 02:23:09 +02:00
Code Issues Packages Projects Releases Wiki Activity
Files
deedfbefe267adcfbfea483933aa3210e69402c1
yosys/docs
T
History
Gary Wong 4ffd05af6f verilog: add support for SystemVerilog string literals. 
Differences are new escape sequences (including escaped newline
continuations and hex escapes) and triple-quoted literals.
2025-08-11 13:34:10 +02:00
..
source
verilog: add support for SystemVerilog string literals.
2025-08-11 13:34:10 +02:00
tests
docs: Fix macro_commands
2024-05-10 09:51:37 +12:00
util
Reapply "Add groups to command reference"
2025-08-06 13:52:12 +12:00
.gitignore
Reapply "Add groups to command reference"
2025-08-06 13:52:12 +12:00
Makefile
Reapply "Add groups to command reference"
2025-08-06 13:52:12 +12:00