Claire Wolf cef607c8b7 Add log_experimental() and experimental() API and "yosys -x" ... Signed-off-by: Claire Wolf <clifford@clifford.at>		2020-01-27 18:27:47 +01:00
..
arria10gx	synth_intel: a10gx -> arria10gx	2019-12-10 13:48:10 +00:00
common	intel: Map M9K BRAM only on families that have it	2019-07-23 18:11:11 +01:00
cyclone10lp	synth_intel: cyclone10 -> cyclone10lp	2019-12-10 13:47:58 +00:00
cycloneiv	…
cycloneive	…
cyclonev	Fixing issues in CycloneV cell sim	2019-04-11 19:59:03 -05:00
max10	…
Makefile.inc	synth_intel: a10gx -> arria10gx	2019-12-10 13:48:10 +00:00
synth_intel.cc	Add log_experimental() and experimental() API and "yosys -x"	2020-01-27 18:27:47 +01:00