luke/yosys
1
0
Fork 0
mirror of https://github.com/YosysHQ/yosys.git synced 2026-09-05 19:36:55 +02:00
Code Issues Packages Projects Releases Wiki Activity
Files
dcb9c0d7af91ccbd189f46bb282e433a0f82eafe
yosys/passes
T
History
Emil J. Tywoniak bb9f7f8abe proc: point cases and flops at the statements they came from 
A CaseRule takes the location of its case item, so the $eq that decodes it
lands on the compare rather than on the block, and a mux keeps the fused
action locations it was given instead of inheriting the case's.

A flop fuses the process location with the locations of the wires it drives.
2026-08-25 12:42:12 +02:00
..
cmds
rtlil: replace SigSig actions with new type SyncAction
2026-08-25 12:41:46 +02:00
equiv
passes: rework passes that search, rekey or cross name pools
2026-08-13 18:15:58 +02:00
fsm
passes: rework passes that search, rekey or cross name pools
2026-08-13 18:15:58 +02:00
hierarchy
rtlil: intern source locations in a per-design SrcPool
2026-08-25 11:40:52 +02:00
memory
rtlil: intern source locations in a per-design SrcPool
2026-08-25 11:40:52 +02:00
opt
rtlil: intern source locations in a per-design SrcPool
2026-08-25 11:40:52 +02:00
pmgen
passes: trivial twine damage
2026-08-13 18:15:58 +02:00
proc
proc: point cases and flops at the statements they came from
2026-08-25 12:42:12 +02:00
sat
rtlil: intern source locations in a per-design SrcPool
2026-08-25 11:40:52 +02:00
techmap
rtlil: replace SigSig actions with new type SyncAction
2026-08-25 12:41:46 +02:00
tests
passes: rework passes that search, rekey or cross name pools
2026-08-13 18:15:58 +02:00
CMakeLists.txt
Migrate build system to CMake
2026-06-03 08:58:10 +00:00