mirror of https://github.com/YosysHQ/yosys.git
64 lines
2.3 KiB
Plaintext
64 lines
2.3 KiB
Plaintext
design -reset
|
|
read_verilog <<EOT
|
|
module top(input [7:0] a, input [7:0] b, output [7:0] y);
|
|
assign y = a & b;
|
|
endmodule
|
|
EOT
|
|
hierarchy -check -top top
|
|
proc; opt -fast
|
|
logger -expect log "ABC: .*i/o = +16/ +8" 2
|
|
logger -expect log "ABC: Warning: The network is combinational\." 1
|
|
logger -expect log "ABC: Networks are equivalent\." 1
|
|
logger -expect warning "Wire top\.\$lit[0-9]+ is used but has no driver\." 8
|
|
logger -expect error "Found 8 problems in 'check -assert'" 1
|
|
abc_new -script "+&scorr;&sweep;&dc2;&dch,-f;&nf,{D}" -liberty ../../examples/cmos/cmos_cells.lib
|
|
check -assert
|
|
|
|
design -reset
|
|
read_verilog <<EOT
|
|
module top(input [3:0] a, input [3:0] b, output [3:0] y);
|
|
assign y = a ^ b;
|
|
endmodule
|
|
EOT
|
|
hierarchy -check -top top
|
|
proc; opt -fast
|
|
logger -expect log "ABC: .*i/o = +8/ +4" 2
|
|
logger -expect log "ABC: Warning: The network is combinational\." 1
|
|
logger -expect log "ABC: Networks are equivalent\." 1
|
|
logger -expect warning "Wire top\.\$lit[0-9]+ is used but has no driver\." 4
|
|
logger -expect error "Found 4 problems in 'check -assert'" 1
|
|
abc_new -script "+&scorr;&sweep;&dc2;&dch,-f;&nf,{D}" -liberty ../../examples/cmos/cmos_cells.lib
|
|
check -assert
|
|
|
|
design -reset
|
|
read_verilog <<EOT
|
|
module top(input [7:0] a, output y);
|
|
assign y = &a;
|
|
endmodule
|
|
EOT
|
|
hierarchy -check -top top
|
|
proc; opt -fast
|
|
logger -expect log "ABC: .*i/o = +8/ +1" 2
|
|
logger -expect log "ABC: Warning: The network is combinational\." 1
|
|
logger -expect log "ABC: Networks are equivalent\." 1
|
|
logger -expect warning "Wire top\.\$lit[0-9]+ is used but has no driver\." 1
|
|
logger -expect error "Found 1 problems in 'check -assert'" 1
|
|
abc_new -script "+&scorr;&sweep;&dc2;&dch,-f;&nf,{D}" -liberty ../../examples/cmos/cmos_cells.lib
|
|
check -assert
|
|
|
|
design -reset
|
|
read_verilog <<EOT
|
|
module top(input [3:0] a, input [3:0] b, output [3:0] sum, output cout);
|
|
assign {cout, sum} = a + b;
|
|
endmodule
|
|
EOT
|
|
hierarchy -check -top top
|
|
proc; opt -fast
|
|
logger -expect log "ABC: .*i/o = +8/ +5" 2
|
|
logger -expect log "ABC: Warning: The network is combinational\." 1
|
|
logger -expect log "ABC: Networks are equivalent\." 1
|
|
logger -expect warning "Wire top\.\$lit[0-9]+ is used but has no driver\." 5
|
|
logger -expect error "Found 5 problems in 'check -assert'" 1
|
|
abc_new -script "+&scorr;&sweep;&dc2;&dch,-f;&nf,{D}" -liberty ../../examples/cmos/cmos_cells.lib
|
|
check -assert
|