mirror of https://github.com/YosysHQ/yosys.git
15 lines
539 B
Plaintext
15 lines
539 B
Plaintext
read_verilog <<EOT
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module top(input a, output y); assign y = a; endmodule
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EOT
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hierarchy -check -top top
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proc; opt -fast
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logger -expect log "ABC: .*i/o = +1/ +1" 3
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logger -expect log "ABC: Warning: The network is combinational\." 1
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logger -expect warning "Feature 'abc_new' is experimental" 1
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logger -expect warning "Feature 'write_xaiger2' is experimental" 1
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logger -expect warning "Feature 'read_xaiger2' is experimental" 1
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logger -expect error "Missing mapping \(no 'M' section\)" 1
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abc_new -liberty ../../examples/cmos/cmos_cells.lib
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