mirror of https://github.com/YosysHQ/yosys.git
117 lines
2.3 KiB
Plaintext
117 lines
2.3 KiB
Plaintext
log -header "Interleaved mux/add chain pushes muxes to the end"
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log -push
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design -reset
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read_verilog <<EOF
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module top (
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input wire s0,
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input wire s1,
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input wire s2,
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input wire [7:0] a,
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input wire [7:0] b,
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input wire [7:0] c,
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input wire [7:0] d,
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input wire [7:0] e,
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output wire [7:0] y
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);
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wire [7:0] m0;
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wire [7:0] a0;
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wire [7:0] m1;
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wire [7:0] a1;
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assign m0 = s0 ? b : a;
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assign a0 = m0 + c;
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assign m1 = s1 ? a0 : d;
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assign a1 = m1 + e;
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assign y = s2 ? a1 : a;
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endmodule
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EOF
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proc
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check -assert
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# Check equivalence after mux push
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equiv_opt -assert muxpush -limit 1 -types $add
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# After the pass, no $add should have a $mux driving its inputs
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design -load postopt
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select -set add_fanin t:$add %ci*
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select -set mux_cells t:$mux t:$ternary
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select -assert-count 0 @add_fanin @mux_cells %i
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design -reset
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log -pop
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log -header "Negative case: fanout limit blocks push"
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log -push
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design -reset
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read_verilog <<EOF
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module top (
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input wire s0,
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input wire [7:0] a,
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input wire [7:0] b,
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input wire [7:0] c,
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input wire [7:0] d,
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output wire [7:0] y0,
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output wire [7:0] y1
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);
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wire [7:0] m0;
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assign m0 = s0 ? b : a;
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assign y0 = m0 + c;
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assign y1 = m0 + d;
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endmodule
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EOF
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proc
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check -assert
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# Check equivalence after mux push (should not apply due to fanout>1)
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equiv_opt -assert muxpush -limit 1 -types $add
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# Mux still drives add inputs due to fanout limit
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design -load postopt
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select -set add_fanin t:$add %ci*
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select -set mux_cells t:$mux t:$ternary
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select -assert-count 1 @add_fanin @mux_cells %i
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design -reset
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log -pop
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log -header "Push with fanout limit > 1"
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log -push
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design -reset
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read_verilog <<EOF
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module top (
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input wire s0,
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input wire [7:0] a,
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input wire [7:0] b,
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input wire [7:0] c,
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input wire [7:0] d,
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output wire [7:0] y0,
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output wire [7:0] y1
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);
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wire [7:0] m0;
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wire [7:0] a0;
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assign m0 = s0 ? b : a;
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assign a0 = m0 + c;
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assign y0 = a0;
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assign y1 = m0 + d;
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endmodule
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EOF
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proc
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check -assert
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# Check equivalence after mux push (allowed due to fanout limit)
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equiv_opt -assert muxpush -limit 2 -types $add
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# Both adders should be pushed with fanout limit > 1
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design -load postopt
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select -set add_fanin t:$add %ci*
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select -set mux_cells t:$mux t:$ternary
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select -assert-count 0 @add_fanin @mux_cells %i
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design -reset
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log -pop
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