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mirror of https://github.com/YosysHQ/yosys.git synced 2026-09-03 19:19:48 +02:00
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dbf2bc3b1dfe0a316e33ada2abb99fa65c8e0616
yosys/tests/proc
T
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Emil J. Tywoniak 01fd72520f proc_rom: test src attribute on memories
2024-07-29 10:13:45 +02:00
..
.gitignore
proc_clean: fix order of switch insertion.
2019-08-19 16:44:23 +00:00
bug2619.ys
proc_dff: Fix emitted FF when a register is not assigned in async reset
2021-03-08 17:01:43 +01:00
bug2656.ys
proc_arst: Add special-casing of clock signal in conditionals.
2021-03-15 17:17:29 +01:00
bug2962.ys
proc_prune: Make assign removal and promotion per-bit, remember promoted bits.
2021-08-14 15:26:11 +02:00
bug_1268.v
proc_clean: fix order of switch insertion.
2019-08-19 16:44:23 +00:00
bug_1268.ys
proc_clean: fix order of switch insertion.
2019-08-19 16:44:23 +00:00
clean_undef_case.ys
proc_clean: only consider fully-defined switch operands too.
2023-08-12 02:46:31 +02:00
proc_rom.ys
proc_rom: test src attribute on memories
2024-07-29 10:13:45 +02:00
rmdead.v
proc_rmdead: use explicit pattern set when there are no wildcards
2021-07-29 20:55:59 -04:00
rmdead.ys
proc_rmdead: use explicit pattern set when there are no wildcards
2021-07-29 20:55:59 -04:00
run-test.sh
tests: use /usr/bin/env for bash.
2023-08-12 11:59:39 +10:00
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