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mirror of https://github.com/YosysHQ/yosys.git synced 2026-09-07 12:21:16 +02:00
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db33b1e535f5ee93dba9ee1cc181b91c482a4dee
yosys/passes
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Marcelina Kościelnicka db33b1e535 opt_dff: Don't mutate muxes while ModWalker is active.
2022-01-28 08:55:56 +01:00
..
cmds
bugpoint: avoid infinite loop between -connections and -wires.
2021-12-15 08:17:02 +00:00
equiv
Fixing old e-mail addresses and deadnames
2021-06-08 00:39:36 +02:00
fsm
Fixing old e-mail addresses and deadnames
2021-06-08 00:39:36 +02:00
hierarchy
verilog: use derived module info to elaborate cell connections
2021-10-25 18:25:50 -07:00
memory
memory_bram: Make use of new mem emulation functions to map more RAMs.
2022-01-27 19:31:27 +01:00
opt
opt_dff: Don't mutate muxes while ModWalker is active.
2022-01-28 08:55:56 +01:00
pmgen
Make it work on all
2021-11-05 10:51:58 +01:00
proc
proc_dff: Emit $aldff.
2021-10-27 14:14:24 +02:00
sat
FfData: some refactoring.
2021-10-07 04:24:06 +02:00
techmap
sta: very crude static timing analysis pass
2021-11-25 17:20:27 +01:00
tests
Fixing old e-mail addresses and deadnames
2021-06-08 00:39:36 +02:00
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