Eddie Hung db09e96dff test: ice40_dsp test to read +/ice40/cells_sim.v for default params

2020-04-22 16:35:35 -07:00

..

anlogic

Simplify breaking tests/arch/*/fsm.ys tests

2020-03-20 11:25:17 -07:00

common

ecp5: add support for both 1364.1 and LSE RAM/ROM attributes.

2020-02-06 16:52:51 +00:00

ecp5

tests: remove write_ilang

2020-04-20 15:42:29 -07:00

efinix

Simplify breaking tests/arch/*/fsm.ys tests

2020-03-20 11:25:17 -07:00

gowin

Add opt_lut_ins pass. (#1673)

2020-02-03 14:57:17 +01:00

ice40

test: ice40_dsp test to read +/ice40/cells_sim.v for default params

2020-04-22 16:35:35 -07:00

intel_alm

synth_intel_alm: alternative synthesis for Intel FPGAs

2020-04-15 11:40:41 +02:00

xilinx

xilinx: xilinx_dffopt to read cells_sim.v; fix test

2020-04-22 16:25:23 -07:00

run-test.sh

tests: extend tests/arch/run-tests.sh for defines

2020-03-05 08:08:32 -08:00