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mirror of https://github.com/YosysHQ/yosys.git synced 2026-10-06 18:13:40 +02:00
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da0778350bf472b9a46068051753625a62d5ddb7
yosys/backends
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Yehowshua Immanuel da0778350b more reasonable numbers for memory
2020-06-04 17:00:04 -04:00
..
aiger
Merge pull request #2077 from YosysHQ/eddie/abc9_dff_improve
2020-06-04 08:15:25 -07:00
blif
kernel: big fat patch to use more ID::*, otherwise ID(*)
2020-04-02 09:51:32 -07:00
btor
Add printf format attributes to btorf/infof helper functions
2020-06-04 15:53:28 +02:00
cxxrtl
cxxrtl: make logging a little bit nicer.
2020-05-26 21:37:32 +00:00
edif
Improve net priorities in EDIF back-end
2020-04-21 12:35:25 +02:00
firrtl
Add flooring modulo operator
2020-05-28 22:59:03 +02:00
ilang
Preserve 'signed'-ness of a verilog wire through RTLIL
2020-04-27 09:44:24 -07:00
intersynth
Clean up pseudo-private member usage in backends/intersynth/intersynth.cc.
2020-04-01 06:32:09 +00:00
json
Preserve 'signed'-ness of a verilog wire through RTLIL
2020-04-27 09:44:24 -07:00
protobuf
Add aiger and protobuf backends binary support
2019-09-28 09:51:48 +02:00
simplec
kernel: big fat patch to use more ID::*, otherwise ID(*)
2020-04-02 09:51:32 -07:00
smt2
more reasonable numbers for memory
2020-06-04 17:00:04 -04:00
smv
Add flooring division operator
2020-05-28 22:59:04 +02:00
spice
kernel: use more ID::*
2020-04-02 07:14:08 -07:00
table
Add "whitebox" attribute, add "read_verilog -wb"
2019-04-18 17:45:47 +02:00
verilog
Add flooring division operator
2020-05-28 22:59:04 +02:00
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