yosys/passes at d97a243c22cd682e4e043bb50d45b4a7cde2ff15 - yosys - Gitea: Git with a cup of tea

luke/yosys

mirror of https://github.com/YosysHQ/yosys.git synced 2026-08-31 10:15:10 +02:00

Files

T

History

Emil J e0d3bbf3c3 Merge pull request #4452 from phsauter/shiftadd-underflow-fix

peepopt: avoid shift-amount underflow

2024-08-19 15:45:46 +02:00

..

Improve libparse encapsulation

2024-08-13 18:47:36 +02:00

equiv_simple: Take FFs into account for driver map

2024-02-21 12:05:52 +01:00

add option to fsm_detect to ignore self-resetting

2023-01-30 16:12:53 +01:00

cost: add model for techmapped cell count, keep_hierarchy pass with -min_cost parameter

2024-07-29 10:26:02 +02:00

memory_map: Explain -iattr better

2024-03-06 15:15:37 +01:00

Merge pull request #4176 from povik/opt_expr-performance

2024-07-15 16:10:25 +02:00

Merge pull request #4452 from phsauter/shiftadd-underflow-fix

2024-08-19 15:45:46 +02:00

proc_rom: Set src on the emitted memory

2024-07-25 23:14:27 +01:00

Set ranges on exported wires in VCD and FST

2024-08-02 15:23:00 +02:00

Improve libparse encapsulation

2024-08-13 18:47:36 +02:00

cost: add model for techmapped cell count, keep_hierarchy pass with -min_cost parameter

2024-07-29 10:26:02 +02:00