yosys/frontends/verilog
David Shah 9e4801cca7 sv: Correct parsing of always_comb, always_ff and always_latch
Signed-off-by: David Shah <dave@ds0.me>
2019-11-21 20:27:19 +00:00
..
.gitignore
Makefile.inc
const2ast.cc
preproc.cc Add check for valid macro names in macro definitions 2019-11-07 13:30:03 +01:00
verilog_frontend.cc Add "verilog_defines -list" and "verilog_defines -reset" 2019-10-21 13:35:56 +02:00
verilog_frontend.h
verilog_lexer.l sv: Correct parsing of always_comb, always_ff and always_latch 2019-11-21 20:27:19 +00:00
verilog_parser.y sv: Correct parsing of always_comb, always_ff and always_latch 2019-11-21 20:27:19 +00:00