This website requires JavaScript.
Explore
Help
Sign In
luke
/
yosys
Watch
1
Star
0
Fork
0
mirror of
https://github.com/YosysHQ/yosys.git
synced
2026-09-05 11:35:20 +02:00
Code
Issues
Packages
Projects
Releases
Wiki
Activity
Files
d8e0180ffbf9fe91adf7f822124dc34b8e4e3d00
yosys
/
techlibs
/
sf2
T
History
Miodrag Milanovic
a689342207
Remove trailing whitespaces
2026-06-23 07:24:59 +02:00
..
tests
sf2: add a test for $alu gate
2022-08-31 08:40:44 +02:00
arith_map.v
End of file fix
2026-06-23 07:23:41 +02:00
cells_map.v
sf2: Use dfflegalize.
2020-07-09 21:56:14 +02:00
cells_sim.v
Test fixes for latest iverilog
2022-09-21 15:46:43 +02:00
CMakeLists.txt
Migrate build system to CMake
2026-06-03 08:58:10 +00:00
NOTES.txt
Remove trailing whitespaces
2026-06-23 07:24:59 +02:00
synth_sf2.cc
Add check before flatten in synth_*.
2026-05-05 14:06:58 +02:00