Clifford Wolf 584d2030bf Build Verilog parser with -DYYMAXDEPTH=100000, fixes #906 ...

Signed-off-by: Clifford Wolf <[email protected]>

2019-03-29 16:32:44 +01:00

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aiger

Add author name

2019-03-19 08:52:06 -07:00

ast

Fix mem2reg handling of memories with upto data ports, fixes #888

2019-03-21 22:21:17 +01:00

blif

Add missing "[options]" to read_blif help

2019-02-08 12:41:39 -08:00

ilang

Add "read_ilang -[no]overwrite"

2018-12-23 15:45:09 +01:00

json

Consistent use of 'override' for virtual methods in derived classes.

2018-07-20 23:51:06 -07:00

liberty

Fix typographical and grammatical errors and inconsistencies.

2019-01-02 13:12:17 +00:00

verific

Add "read -verific" and "read -noverific"

2019-03-27 14:03:35 +01:00

verilog

Build Verilog parser with -DYYMAXDEPTH=100000, fixes #906

2019-03-29 16:32:44 +01:00