mirror of https://github.com/YosysHQ/yosys.git
54 lines
1000 B
Verilog
54 lines
1000 B
Verilog
// Copyright 2020-2022 F4PGA Authors
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//
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// Licensed under the Apache License, Version 2.0 (the "License");
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// you may not use this file except in compliance with the License.
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// You may obtain a copy of the License at
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//
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// http://www.apache.org/licenses/LICENSE-2.0
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//
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// Unless required by applicable law or agreed to in writing, software
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// distributed under the License is distributed on an "AS IS" BASIS,
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// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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// See the License for the specific language governing permissions and
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// limitations under the License.
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//
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// SPDX-License-Identifier: Apache-2.0
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module inv (
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output Q,
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input A
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);
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assign Q = A ? 0 : 1;
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endmodule
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module buff (
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output Q,
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input A
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);
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assign Q = A;
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endmodule
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module logic_0 (
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output a
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);
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assign a = 0;
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endmodule
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module logic_1 (
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output a
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);
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assign a = 1;
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endmodule
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(* blackbox *)
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module gclkbuff (
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input A,
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output Z
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);
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assign Z = A;
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endmodule
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