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mirror of https://github.com/YosysHQ/yosys.git synced 2026-09-06 11:59:46 +02:00
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d68c993ed2ea384db4d6af5161b3b36096828499
yosys/passes/techmap
T
History
Clifford Wolf d68c993ed2 Changed more code to the new RTLIL::Wire constructors
2014-07-26 21:30:38 +02:00
..
.gitignore
added .gitignore files
2013-01-05 11:19:11 +01:00
dfflibmap.cc
Manual fixes for new cell connections API
2014-07-26 15:58:23 +02:00
extract.cc
Changed more code to the new RTLIL::Wire constructors
2014-07-26 21:30:38 +02:00
filterlib.cc
Moved dfflibmap from passes/dfflibmap to passes/techmap
2013-10-16 15:32:26 +02:00
hilomap.cc
Manual fixes for new cell connections API
2014-07-26 15:58:23 +02:00
iopadmap.cc
Changed more code to the new RTLIL::Wire constructors
2014-07-26 21:30:38 +02:00
libparse.cc
Fixed dumping of timing() { .. } block in libparse
2014-03-09 15:16:07 +01:00
libparse.h
renamed LibertyParer to LibertyParser
2014-01-14 18:57:47 +01:00
Makefile.inc
Added "make SMALL=1"
2014-07-24 19:03:57 +02:00
simplemap.cc
Manual fixes for new cell connections API
2014-07-26 15:58:23 +02:00
techmap.cc
Changed more code to the new RTLIL::Wire constructors
2014-07-26 21:30:38 +02:00
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