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yosys/techlibs/ecp5
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David Shah 520f1646cf Merge pull request #1563 from YosysHQ/dave/async-prld 
ecp5: Add support for mapping PRLD FFs
2019-12-18 19:42:17 +00:00
..
tests
ecp5: Add simulation equivalence check for Diamond FF implementations
2019-08-30 13:27:36 +01:00
.gitignore
ecp5: Add support for mapping 36-bit wide PDP BRAMs
2019-10-01 13:46:36 +01:00
abc9_5g_nowide.lut
Rename abc_* names/attributes to more precisely be abc9_*
2019-10-04 11:04:10 -07:00
abc9_5g.box
Rename abc_* names/attributes to more precisely be abc9_*
2019-10-04 11:04:10 -07:00
abc9_5g.lut
Rename abc_* names/attributes to more precisely be abc9_*
2019-10-04 11:04:10 -07:00
abc9_map.v
Rename abc_* names/attributes to more precisely be abc9_*
2019-10-04 11:04:10 -07:00
abc9_model.v
Rename abc_* names/attributes to more precisely be abc9_*
2019-10-04 11:04:10 -07:00
abc9_unmap.v
Rename abc_* names/attributes to more precisely be abc9_*
2019-10-04 11:04:10 -07:00
arith_map.v
ecp5: Improve mapping of $alu when BI is used
2019-06-21 09:45:11 +01:00
bram.txt
ecp5: Fix shuffle_enable port
2019-10-01 14:14:46 +01:00
brams_connect.py
ecp5: Add support for mapping 36-bit wide PDP BRAMs
2019-10-01 13:46:36 +01:00
brams_init.py
ecp5: First BRAM type maps successfully
2018-10-10 16:35:19 +01:00
brams_map.v
ecp5: Add support for mapping 36-bit wide PDP BRAMs
2019-10-01 13:46:36 +01:00
cells_bb.v
ecp5: Add ECLKBRIDGECS blackbox
2019-10-11 14:50:33 +01:00
cells_ff.vh
Fix bitwidth mismatch; suppresses iverilog warning
2019-12-11 13:02:07 -08:00
cells_io.vh
ecp5: deduplicate Diamond FD/IFS/OFS/IO primitives.
2019-08-30 10:05:09 +00:00
cells_map.v
ecp5: Add support for mapping PRLD FFs
2019-12-07 13:04:36 +00:00
cells_sim.v
Rename abc_* names/attributes to more precisely be abc9_*
2019-10-04 11:04:10 -07:00
dsp_map.v
ecp5: Bring up to date with mul2dsp changes
2019-08-08 15:14:09 +01:00
ecp5_ffinit.cc
ecp5: Demote conflicting FF init values to a warning
2019-03-04 11:26:20 +00:00
ecp5_gsr.cc
ecp5_gsr: Fix typo
2019-08-31 09:58:46 +01:00
latches_map.v
ecp5: Add latch inference
2018-10-19 15:16:40 +01:00
lutram.txt
synth_ecp5: rename dram to lutram everywhere.
2019-07-16 20:45:12 +00:00
lutrams_map.v
synth_ecp5: rename dram to lutram everywhere.
2019-07-16 20:45:12 +00:00
Makefile.inc
Makefile: don't assume python is called python3
2019-10-19 14:04:52 +08:00
synth_ecp5.cc
ecp5: Add support for mapping PRLD FFs
2019-12-07 13:04:36 +00:00