Claire Wolf b597f85b13 Merge pull request #1718 from boqwxp/precise_locations ...

Closes #1717. Add more precise Verilog source location information to AST and RTLIL nodes.

2020-03-03 08:38:32 -08:00

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aiger

tests/aiger: Add missing .gitignore

2020-02-15 19:52:21 +01:00

arch

Merge pull request #1718 from boqwxp/precise_locations

2020-03-03 08:38:32 -08:00

asicworld

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bram

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errors

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fsm

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hana

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liberty

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lut

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memfile

Added 'set -e' into tests/memfile/run-test.sh

2020-02-06 10:45:40 -03:00

memories

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opt

Merge pull request #1576 from YosysHQ/eddie/opt_merge_init

2020-02-05 14:56:26 -08:00

opt_share

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proc

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realmath

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rpc

make rpc frontend unix socket test less fragile

2020-02-13 20:52:22 +01:00

sat

Merge pull request #1638 from YosysHQ/eddie/fix1631

2020-02-05 19:31:18 +01:00

share

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simple

Make SV2017 compliant courtesy of @wsnyder

2019-12-12 07:34:07 -08:00

simple_abc9

Update simple_abc9 tests

2020-02-27 10:17:29 -08:00

smv

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sva

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svinterfaces

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svtypes

add attributes for enumerated values in ilang

2020-02-17 04:42:42 -05:00

techmap

iopadmap: Look harder for already-present buffers. (#1731)

2020-03-02 21:40:09 +01:00

tools

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unit

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various

Merge pull request #1718 from boqwxp/precise_locations

2020-03-03 08:38:32 -08:00

vloghtb

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