Robert O'Callahan 1260fda83a Add 'init' attributes to RTLIL fuzzing

2026-03-06 02:20:08 +00:00

..

.gitignore

added more .gitignore files (make test)

2013-01-05 11:35:52 +01:00

autotest.mk

Update cells supported for verilog to FIRRTL conversion.

2019-02-15 11:14:17 -08:00

autotest.sh

Missed an iverilog

2025-12-15 10:31:17 +13:00

cmp_tbdata.c

Fix for modules with big interfaces.

2016-09-13 13:13:27 +03:00

profiler.pl

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rtlil-fuzz-grammar.json

Add 'init' attributes to RTLIL fuzzing

2026-03-06 02:20:08 +00:00

txt2tikztiming.py

Switched to Python 3

2015-08-22 09:59:33 +02:00

vcd2txt.pl

Added vcd2txt.pl and txt2tikztiming.py (tests/tools/...)

2014-02-19 12:40:49 +01:00

vcdcd.pl

Fixes in vcdcd.pl for newer Perl versions

2021-10-19 10:56:43 +02:00