mirror of
https://github.com/YosysHQ/yosys.git
synced 2026-09-06 20:12:09 +02:00
Zachary Snow
0d8e5d965f
- Signed cell outputs are sign extended when bound to larger wires - Signed connections are sign extended when bound to larger cell inputs - Sign extension is performed in hierarchy and flatten phases - genrtlil indirects signed constants through signed wires - Other phases producing RTLIL may need to be updated to preserve signedness information - Resolves #1418 - Resolves #2265