yosys/tests/sat/asserts.ys at d4ff5b2d007c73cd95fa61bafdb65a47796014d9 - yosys - Gitea: Git with a cup of tea

luke/yosys

mirror of https://github.com/YosysHQ/yosys.git synced 2026-09-04 19:31:00 +02:00

Files

T

Clifford Wolf 482d9208aa Added read_verilog -sv options, added support for bit, logic,

allways_ff, always_comb, and always_latch

2014-06-12 11:54:20 +02:00

4 lines

110 B

Plaintext

Raw Blame History

	`read_verilog -sv asserts.v`
	`hierarchy; proc; opt`
	`sat -verify -seq 1 -set-at 1 rst 1 -tempinduct -prove-asserts`