yosys/techlibs/common
Jannis Harder aa7e7df19f simlib: Simplify recently changed $mux model
The use of a procedural continuous assignment introduced in #3526 was
unintended and is completely unnecessary for the actual change of that
PR.
2022-10-28 19:48:00 +02:00
..
.gitignore
Makefile.inc Add smtmap.v describing the smt2 backend's behavior for undef bits 2022-10-20 15:48:18 +02:00
abc9_map.v
abc9_model.v
abc9_unmap.v
adff2dff.v
cellhelp.py
cells.lib
cmp2lcu.v
cmp2lut.v
dff2ff.v
gate2lut.v
gen_fine_ffs.py
mul2dsp.v
pmux2mux.v
prep.cc
simcells.v
simlib.v simlib: Simplify recently changed $mux model 2022-10-28 19:48:00 +02:00
smtmap.v Add smtmap.v describing the smt2 backend's behavior for undef bits 2022-10-20 15:48:18 +02:00
synth.cc Add -no-rw-check option to memory_dff + memory + synth_{ice40,ecp5,gowin}. 2022-06-02 23:16:12 +02:00
techmap.v Add $bmux and $demux cells. 2022-01-28 23:34:41 +01:00