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mirror of https://github.com/YosysHQ/yosys.git synced 2026-10-06 10:03:36 +02:00
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d320e750877a6cf8d5993da6d2cd121fe5b4d78e
yosys/passes/techmap
T
History
Clifford Wolf d320e75087 document "techmap -map %<design-name>"
2014-08-15 02:01:30 +02:00
..
.gitignore
Renamed "stdcells.v" to "techmap.v"
2014-07-31 02:32:00 +02:00
dfflibmap.cc
More cleanups related to RTLIL::IdString usage
2014-08-02 13:19:57 +02:00
extract.cc
Added module->ports
2014-08-14 16:22:52 +02:00
filterlib.cc
Moved dfflibmap from passes/dfflibmap to passes/techmap
2013-10-16 15:32:26 +02:00
hilomap.cc
Renamed port access function on RTLIL::Cell, added param access functions
2014-07-31 16:38:54 +02:00
iopadmap.cc
Renamed port access function on RTLIL::Cell, added param access functions
2014-07-31 16:38:54 +02:00
libparse.cc
Fixed dumping of timing() { .. } block in libparse
2014-03-09 15:16:07 +01:00
libparse.h
renamed LibertyParer to LibertyParser
2014-01-14 18:57:47 +01:00
Makefile.inc
Renamed "stdcells.v" to "techmap.v"
2014-07-31 02:32:00 +02:00
simplemap.cc
More cleanups related to RTLIL::IdString usage
2014-08-02 13:19:57 +02:00
techmap.cc
document "techmap -map %<design-name>"
2014-08-15 02:01:30 +02:00
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