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mirror of https://github.com/YosysHQ/yosys.git synced 2026-09-03 03:13:21 +02:00
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d31c968d76e99d5c7288d0eb844e041bb36aa77d
yosys/techlibs
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History
Clifford Wolf d31c968d76 Fixed typo in greenpak4_counters.cc
2016-03-31 08:00:59 +02:00
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common
Added more cell help messages
2016-03-29 15:14:43 +02:00
greenpak4
Fixed typo in greenpak4_counters.cc
2016-03-31 08:00:59 +02:00
ice40
Work around DDR dout sim glitches in ice40 SB_IO sim model
2016-02-07 11:19:48 +01:00
xilinx
Added black box modules for all the 7-series design elements (as listed in ug953)
2016-03-19 11:09:10 +01:00
.gitignore
added .gitignore files
2013-01-05 11:19:11 +01:00
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