yosys/techlibs/intel_alm/common
Dan Ravensloft 1a07b330f8 intel_alm: Add multiply signedness to cells
Quartus assumes unsigned multiplication by default, breaking signed
multiplies, so add an input signedness parameter to the MISTRAL_MUL*
cells to propagate to Quartus' <family>_mac cells.
2020-08-26 22:50:16 +02:00
..
abc9_map.v
abc9_model.v
abc9_unmap.v
alm_map.v
alm_sim.v intel_alm: add additional ABC9 timings 2020-07-23 11:57:07 +01:00
arith_alm_map.v
bram_m10k.txt intel_alm: direct M10K instantiation 2020-07-27 15:39:06 +02:00
bram_m20k.txt
bram_m20k_map.v
dff_map.v synth_intel_alm: Use dfflegalize. 2020-07-04 22:56:16 +02:00
dff_sim.v intel_alm: add additional ABC9 timings 2020-07-23 11:57:07 +01:00
dsp_map.v intel_alm: Add multiply signedness to cells 2020-08-26 22:50:16 +02:00
dsp_sim.v intel_alm: Add multiply signedness to cells 2020-08-26 22:50:16 +02:00
lutram_mlab.txt
megafunction_bb.v intel_alm: Add multiply signedness to cells 2020-08-26 22:50:16 +02:00
mem_sim.v intel_alm: direct M10K instantiation 2020-07-27 15:39:06 +02:00
quartus_rename.v intel_alm: Add multiply signedness to cells 2020-08-26 22:50:16 +02:00