Ethan Mahintorabi d2a04cca0e write_verilog: Making sure BUF cells are converted to expressions. ...

These were previously not being converted correctly leading to yosys
internal cells being written to my netlist.

Signed-off-by: Ethan Mahintorabi <[email protected]>

2024-01-25 17:00:05 +00:00

..

aiger

Merge pull request #3778 from jix/yw_clk2fflogic

2023-06-05 16:15:04 +02:00

blif

Slightly adjust the wording of "write_blif" help

2023-07-10 12:41:43 +02:00

btor

tests: use /usr/bin/env for bash.

2023-08-12 11:59:39 +10:00

cxxrtl

cxxrtl: fix typo in codegen for async set/clear.

2024-01-24 16:30:01 +00:00

edif

Improve EDIF lib_cell_ports scan

2023-06-20 10:42:05 +02:00

firrtl

tests: use /usr/bin/env for bash.

2023-08-12 11:59:39 +10:00

intersynth

Intersynth URL

2021-06-09 12:42:52 +02:00

jny

Drop stray 'cellaigs.h' include from backend passes

2023-07-10 12:45:03 +02:00

json

Fixes for some of clang scan-build detected issues

2023-01-17 12:58:08 +01:00

rtlil

backends/rtlil: Do not shorten a value with z bits to 'x

2023-01-29 14:02:25 +01:00

simplec

tests: use /usr/bin/env for bash.

2023-08-12 11:59:39 +10:00

smt2

Merge pull request #3887 from kivikakk/env-bash

2023-12-18 16:33:35 +01:00

smv

tests: use /usr/bin/env for bash.

2023-08-12 11:59:39 +10:00

spice

Fixing old e-mail addresses and deadnames

2021-06-08 00:39:36 +02:00

table

Fixing old e-mail addresses and deadnames

2021-06-08 00:39:36 +02:00

verilog

write_verilog: Making sure BUF cells are converted to expressions.

2024-01-25 17:00:05 +00:00