mirror of
https://github.com/YosysHQ/yosys.git
synced 2026-10-06 10:03:36 +02:00
11 lines
193 B
Plaintext
11 lines
193 B
Plaintext
read_verilog <<EOT
|
|
module top(input en, s, d, output reg q);
|
|
wire a = s ? a : d;
|
|
always @*
|
|
if (en)
|
|
q = a;
|
|
endmodule
|
|
EOT
|
|
logger -expect error "Found logic loop through \$mux cell" 1
|
|
proc
|