mirror of https://github.com/YosysHQ/yosys.git
153 lines
2.8 KiB
Plaintext
153 lines
2.8 KiB
Plaintext
log -header "Should not be turned into a tree"
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log -push
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design -reset
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read_verilog <<EOF
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module top (
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input wire a,
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input wire b,
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input wire c,
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input wire d,
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output wire x,
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output wire y,
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output wire z
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);
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assign x = a & b;
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assign y = x & c;
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assign z = y & d;
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endmodule
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EOF
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check -assert
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# Check equivalence after opt_expand
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# equiv_opt -assert opt_balance_tree
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opt_balance_tree
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# TODO check design to make sure that it is not turned into a tree
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# design -load postopt
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design -reset
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log -pop
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log -header "With a cell"
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log -push
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design -reset
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read_verilog <<EOF
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module top (
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input wire a,
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input wire b,
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input wire c,
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input wire d,
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output wire x,
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output wire y,
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output wire z
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);
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wire temp;
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assign y = ~temp;
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assign x = a & b;
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assign temp = x & c;
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assign z = temp & d;
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endmodule
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EOF
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check -assert
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# Check equivalence after opt_expand
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# equiv_opt -assert opt_balance_tree
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opt_balance_tree
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# TODO check design to make sure that it is not turned into a tree
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# Note: this one already worked, just including here for completeness
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# design -load postopt
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design -reset
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log -pop
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log -header "Word out port"
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log -push
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design -reset
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read_verilog <<EOF
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module top (
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input wire a,
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input wire b,
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input wire c,
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input wire d,
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output wire [2:0] x
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);
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assign x[0] = a & b;
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assign x[1] = x[0] & c;
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assign x[2] = x[1] & d;
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endmodule
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EOF
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check -assert
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# Check equivalence after opt_expand
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# equiv_opt -assert opt_balance_tree
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opt_balance_tree
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# TODO check design to make sure that it is not turned into a tree
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# Note: this one already worked, just including here for completeness
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# design -load postopt
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design -reset
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log -pop
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log -header "Fanout going to multiple outputs"
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log -push
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design -reset
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read_verilog <<EOF
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module top (
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input wire a,
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input wire b,
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input wire c,
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input wire d,
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output wire [2:0] x,
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output wire y
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);
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assign x[0] = a & b;
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assign x[1] = x[0] & c;
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assign x[2] = x[1] & d;
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assign y = x[1];
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endmodule
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EOF
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check -assert
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# Check equivalence after opt_expand
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# equiv_opt -assert opt_balance_tree
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opt_balance_tree
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# TODO check design to make sure that it is not turned into a tree
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# Note: this one already worked, just including here for completeness
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# design -load postopt
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design -reset
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log -pop
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log -header "Fanout going to multiple of the same word"
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log -push
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design -reset
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read_verilog <<EOF
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module top (
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input wire a,
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input wire b,
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input wire c,
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input wire d,
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output wire [3:0] x,
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);
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assign x[0] = a & b;
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assign x[1] = x[0] & c;
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assign x[2] = x[1] & d;
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assign x[3] = x[1];
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endmodule
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EOF
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check -assert
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# Check equivalence after opt_expand
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# equiv_opt -assert opt_balance_tree
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opt_balance_tree
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# TODO check design to make sure that it is not turned into a tree
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# Note: this one already worked, just including here for completeness
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# design -load postopt
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design -reset
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log -pop |