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mirror of https://github.com/YosysHQ/yosys.git synced 2026-09-03 19:19:48 +02:00
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d0a41d4f58cacc62a30ec27f33763f637512ff21
yosys/frontends
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Robert O'Callahan 25aafab86b Set port_id for Verific PortBus wires
2025-10-23 20:51:53 +00:00
..
aiger
Remove .c_str() from parameters to log_debug()
2025-09-23 19:10:33 +12:00
aiger2
Remove .c_str() calls from log()/log_error()
2025-09-11 20:59:37 +00:00
ast
verilog: Bufnorm cell backend and frontend support
2025-09-17 14:01:09 +02:00
blif
Merge pull request #4125 from povik/read-blif-gate-ff
2025-09-29 08:21:16 -05:00
json
Use fast path for 32-bit Const integer constructor in more places
2025-09-16 03:17:24 +00:00
liberty
Remove .c_str() calls from parameters to log_header()
2025-09-16 23:00:42 +00:00
rpc
Remove .c_str() from parameters to log_debug()
2025-09-23 19:10:33 +12:00
rtlil
Don't stop parsing sigspec after a {} group.
2025-10-14 21:18:58 +00:00
verific
Set port_id for Verific PortBus wires
2025-10-23 20:51:53 +00:00
verilog
Merge pull request #5315 from YosysHQ/emil/write_rtlil-no-sort
2025-09-22 11:14:39 +02:00
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