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mirror of https://github.com/YosysHQ/yosys.git synced 2026-10-06 18:13:40 +02:00
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d047ca8b11384dfe8f5d4b63ae7b3e6dfa2d6558
yosys/frontends
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Claire Wolf d047ca8b11 Merge pull request #1981 from YosysHQ/claire/fix1837
Clear current_scope when done with RTLIL generation
2020-05-01 14:58:41 +02:00
..
aiger
aigerparse: only define __STDC_FORMAT_MACROS it not already before.
2020-04-07 12:50:31 -07:00
ast
Clear current_scope when done with RTLIL generation, fixes #1837
2020-04-22 14:51:20 +02:00
blif
kernel: big fat patch to use more ID::*, otherwise ID(*)
2020-04-02 09:51:32 -07:00
ilang
ilang, ast: Store parameter order and default value information.
2020-04-21 19:09:00 +02:00
json
Update JSON front-end to process new attr/param encoding
2019-08-01 12:48:22 +02:00
liberty
kernel: big fat patch to use more ID::*, otherwise ID(*)
2020-04-02 09:51:32 -07:00
rpc
ast, rpc: record original name of $paramod\* as \hdlname attribute.
2020-04-18 03:47:28 +00:00
verific
verific: ignore anonymous enums
2020-04-30 07:48:47 -07:00
verilog
Set Verilog source location for explicit blocks (begin ... end).
2020-04-17 06:23:03 +00:00
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