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mirror of https://github.com/YosysHQ/yosys.git synced 2026-10-06 18:13:40 +02:00
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cfddef5d7d265d2260aad2d6ea8595f8b660eb6a
yosys/frontends
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Zachary Snow 4fec3a85cd genrtlil: add width detection for AST_PREFIX nodes
2021-07-29 20:55:31 -04:00
..
aiger
Fixing old e-mail addresses and deadnames
2021-06-08 00:39:36 +02:00
ast
genrtlil: add width detection for AST_PREFIX nodes
2021-07-29 20:55:31 -04:00
blif
Fixing old e-mail addresses and deadnames
2021-06-08 00:39:36 +02:00
json
Fixing old e-mail addresses and deadnames
2021-06-08 00:39:36 +02:00
liberty
Fixing old e-mail addresses and deadnames
2021-06-08 00:39:36 +02:00
rpc
Fix argument handling in connect_rpc
2020-10-19 13:40:57 +02:00
rtlil
rtlil: Make Process handling more uniform with Cell and Wire.
2021-07-12 00:47:34 +02:00
verific
Update to latest verific
2021-07-21 09:46:53 +02:00
verilog
verilog: save and restore overwritten macro arguments
2021-07-28 21:52:16 -04:00
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